1. Field of the Invention
The present invention pertains to the field of thin films for use in integrated circuits, and particularly thin film layered superlattice materials. More specifically, a specialized interface buffer layer enhances the performance of thin film layered superlattice materials.
2. Statement of the Problem
Ferroelectric materials are characterized by their ability to retain an induced polarization state even in the absence of an applied electric field. If the polarization state in one direction is identified as a logic xe2x80x9c0xe2x80x9d polarization state and the polarization state in the opposite direction is identified as a logic xe2x80x9c1xe2x80x9d polarization state, and appropriate circuitry is provided to sense the polarization state, a ferroelectric material can be used as the information storage medium of a high speed nonvolatile computer memory. It is known that such ferroelectric memory device can be made by substituting a ferroelectric material for the dielectric capacitor material of a conventional DRAM capacitor circuit and making appropriate changes in the read and write circuits and manufacturing processes to utilize the ferroelectric film as the information storage medium. See, for example, U.S. Pat. No. 5,784,310 issued Jul. 21, 1998 to Cuchiaro et al. This substitution converts the DRAM cell to a nonvolatile memory cell due to long-term retention of an induced polarization state in the ferroelectric material even in the absence of an applied field. It is also possible to make a ferroelectric memory cell consisting of a single field effect transistor due to the nonvolatile polarization state of ferroelectric thin films, as described in U.S. Pat. No. 5,780,886 issued to Yamanobe et al.
A problem arising in the use of ferroelectric memory devices is that point charge defects at the thin film layered superlattice material layer surfaces have the effect of screening the applied field due to the presence of induced charge at the thin film surface creating a field opposite to the applied field. Thus, some of the interior ferroelectric domains of the crystal are never exposed to a field having sufficient magnitude to completely polarize the domains. The polarization performance of the ferroelectric memory devices suffer as a result of this field screening.
The most serious problems associated with screening, i.e., ferroelectric fatigue, leakage, and imprint problems, can be largely overcome through the use of layered thin film superlattice materials, as reported in U.S. Pat. No. 5,784,310 issued Jul. 21, 1998 to Cuchiaro et al. Ferroelectric perovskite-like layered thin film superlattice materials are a known class of self-ordering crystals, and have been used in thin films suitable for use in integrated circuits, e.g., as reported in U.S. Pat. No. 5,519,234 issued May 21, 1996 to Araujo et al. The term xe2x80x9cperovskite-likexe2x80x9d usually refers to a number of interconnected oxygen octahedra. A primary cell is typically formed of an oxygen octahedral positioned within a cube that is defined by large A-site metals where the oxygen atoms occupy the planar face centers of the cube and a small B-site element occupies the center of the cube. In some instances, the oxygen octahedra may be preserved in the absence of A-site elements.
The thin film layered superlattice materials layers are characterized by an ability to find thermodynamic stability in layered structures. Disordered solutions of superlattice-forming metals, when exposed to thermal treatments, spontaneously form a single layered superlattice material compound having intercollated layers of perovskite-like octahedrons and a superlattice generator such as bismuth oxide. The resultant self-ordered structure forms a superlattice by virtue of a dual periodicity corresponding to the repeated layers. The layered thin film superlattice materials have this self-ordering ability and, consequently, are distinct from semiconductor heterolattices which require the deposition of each layer in a separate deposition step.
The thin film layered superlattice materials, while much superior than prior art materials, still present problems relating to integration into conventional integrated circuit processes. For example, crystallization of the best of the layered superlattice materials require high temperatures that can damage conventional integrated circuit components such as wiring layers and semiconductors. In addition, diffusion of chemical elements between these materials and conventional integrated circuit materials degrades both the layered materials and the conventional materials. Further, the interfaces between the layered superlattice materials and conventional integrated circuit materials are often problematic: evaporation of highly volatile elements of the layered superlattice material, such as bismuth, can create deficiency of the volatile element in the layered superlattice material, leading to defects. Screening, surface roughness, and adhesion problems can also occur at these interfaces. Because of such problems, current ferroelectric memories are usually made with the ferroelectric material isolated from the conventional materials by a thick layer of an insulator. This, of course, increases the bulk of the memory and decreases the density of the memory.
Bismuth oxide and Sr3Bi2O6 buffer layers between the layered superlattice materials and the conventional integrated circuit components have been proposed as a solution to the bismuth deficiency problem. See H. Yamawaki, S. Miyagaki, T. Eshita and Y. Arimoto, xe2x80x9cUltra Thin SrBi2Ta2O9 Ferroelectric Films Grown By Liquid Source CVD Using BiOx Buffer Layers, in Extended Abstracts of the 1998 Inter. Conf. on Solid State Devices and Materials, 1998, pp. 102-103 and U.S. Pat. No. 6,194,227 B1 issued Feb. 27, 2001 to Takashi Hase. While analysis of the material has shown that such buffer layers solve the bismuth deficiency problem, the other problems mentioned above remained, and the electrical properties of the layered superlattice materials made with such buffer layers were not significantly improved.
It is also known that the polarizability of layered thin film superlattice materials is reduced if stoichiometric precursors are used, since some elements, such as bismuth, are more volatile and are disproportionately removed from the materials during drying and annealing. Therefore, precursors using excess amounts of these volatile elements are often used so that, after drying and annealing, the resulting material is approximately stoichiometric. Bismuth gradients have also been used to obtain essentially stoichiometric final layered superlattice materials. See, for example, U.S. Pat. No. 5,439,845 issued Aug. 8, 1995 to Watanabe et al. While the devices using a gradient show enhanced polarizability, they also must be relatively thick because of the multiple layers, resulting in lower density of the thin film superlattice material memory.
There remains a need to obtain greater residual polarization values and improve the interface between the thin film superlattice material layers and the conventional materials. The solution of these problems will result in increasing the density of thin film superlattice material memories and other integrated circuits that contain thin film superlattice materials as well as more reliable memories.
The present invention advances the art and overcomes the aforementioned problems by providing improved thin film ferroelectric devices having an enhanced magnitude of residual polarization. These improvements derive from the use of an interface buffer layer between the electrode and the thin film superlattice material layer. An integrated circuit memory device according to the invention includes a substrate supporting a thin film superlattice material layer. The thin film superlattice material layer is xe2x80x9cinterfacedxe2x80x9d on one or both the top and bottom side by an interface buffer layer. Preferably, the interface buffer layer is a non-ferroelectric material. An interface buffer layer is preferably placed directly on top of the bottom electrode or directly below the top electrode, or both. The interface buffer layer is preferably at least 3 nanometers (nm) thick, and preferably resides in direct contact with both the electrode and the first thin film superlattice material layer. Preferably, the interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. Here, a xe2x80x9csimple oxidexe2x80x9d is an oxide that does not have a layered structure, but rather has a crystalline structure consisting of a single repeated unit cell. The simple oxide not including bismuth can be one including a plurality of metals or one including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals. xe2x80x9cDifferentxe2x80x9d within the above context means that either the chemical elements or the stoichiometry with respect to the A-site and B-site elements is different in the second layered superlattice material as compared to the first layered superlattice material. xe2x80x9cDifferentxe2x80x9d does not include the situation in which the amount of bismuth or other layered superlattice generator material is the only difference.
The interface buffer layer preferably ranges from 3 nm to 30 nm in thickness, with the most preferred thicknesses ranging from 5 nm to 20 nm to provide adequate defect compensation while being thin enough to avoid significant problems with parasitic capacitance.
The invention provides an integrated circuit device including a substrate supporting a first thin film layered superlattice material layer and an electrode, comprising an interface buffer layer interposed between the thin film layered superlattice material layer and the electrode, the interface buffer layer selected from the group consisting of: simple oxides, not including bismuth, of an A-site or a B-site metal; and second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. Preferably, the interface buffer layer is selected from the group consisting of: strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals. Preferably, the interface buffer layer comprises strontium tantalate, bismuth tantalate, strontium niobium tantalate, titanium oxide, or tantalum pentoxide and the layered superlattice material comprises strontium bismuth tantalate, strontium bismuth niobium tantalate, bismuth titanate, or bismuth lanthanum titanate. Preferably, the first layered superlattice material comprises strontium bismuth tantalum niobate or strontium bismuth tantalate, and the second layered superlattice material comprises strontium bismuth tantalum niobate in which the amount of niobium exceeds the amount of niobium in the first layered superlattice material.
The invention also provides a method of making an integrated circuit memory device, the method comprising the steps of: depositing a first electrode layer on a substrate; depositing a first interface buffer layer on the substrate, the first interface buffer layer selected from the group consisting of: simple oxides, not including bismuth, of an A-site or a B-site metal; and layered superlattice materials; and depositing a thin film layered superlattice material layer adjacent to the thin film interface buffer layer, the thin film layered superlattice material layer being a different material than the first interface buffer layer material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first interface buffer layer material. Preferably, the first interface buffer layer is selected from the group consisting of: strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.
The invention further provides a method of making an integrated circuit memory device, the method comprising the steps of: depositing an electrode layer on the substrate; with the substrate in a deposition chamber, depositing a first interface buffer layer on the substrate, the interface buffer layer selected from the group consisting of simple oxides, not including bismuth, of an A-site or a B-site metal; and without removing the substrate from the deposition chamber, switching on a superlattice generator metal source supply to deposit a thin film layered superlattice material layer including the superlattice generator metal adjacent to the thin film layered superlattice material layer. Preferably, the method further includes the step of switching off the superlattice generator metal source supply to deposit a second interface buffer layer on the thin film layered superlattice material layer, the interface buffer layer selected from the group consisting of simple oxides, not including bismuth, of an A-site or a B-site metal; and depositing an electrode layer adjacent the interface buffer layer.
In addition, the invention provides a method of making an integrated circuit memory device, the method comprising the steps of: depositing a first electrode layer on a substrate; depositing a first interface buffer layer on the substrate, the first interface buffer layer selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals; baking the integrated circuit device at a soft bake temperature; depositing a thin film layered superlattice material layer adjacent the interface buffer layer, the thin film layered superlattice material layer selected from the group consisting of strontium bismuth tantalate, strontium bismuth niobate, strontium bismuth niobium tantalate, bismuth titanate, and bismuth lanthanum titanate; baking the integrated circuit device at a soft bake temperature; and annealing one or more of the layers. Preferably, the method also includes the steps of: depositing a second interface buffer layer adjacent the thin film superlattice material layer, the second interface buffer layer selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals; baking the integrated circuit device at a soft bake temperature; and depositing a second electrode adjacent the second interface buffer layer.
The invention also provides a method of making an integrated circuit memory device, the method comprising the steps of: depositing a first electrode layer on a substrate; depositing a first interface buffer layer on the substrate, the first interface buffer layer comprising strontium bismuth tantalum niobate; depositing a thin film layered superlattice material layer adjacent the interface buffer layer, the thin film layered superlattice material layer comprising strontium bismuth tantalate or strontium bismuth tantalum niobate having a lesser amount of niobium than said first interface buffer layer; and annealing the integrated circuit device at a crystallization temperature lower than the crystallization temperature of the layered superlattice material layer without the first interface buffer layer. Preferably, the method further includes the steps of: depositing a second interface buffer layer adjacent the thin film superlattice material layer, the interface buffer layer selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals; depositing a second electrode layer adjacent the interface buffer layer; and annealing one or more of the layers. Preferably, the second interface buffer layer comprises strontium bismuth tantalum niobate having a higher concentration of niobium than the thin film layered superlattice material. Preferably, the strontium bismuth tantalate crystallization temperature ranges from 550xc2x0 C. to 750xc2x0 C.
The use of the interface buffer layer appears to prevent field screening by providing a transition from the ferroelectric to the conductor. It permits very thin film superlattice material devices with excellent ferroelectric properties. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.